Реферат: Процессор. Блок целочисленной арифметики.

                                             1                                                          3            МК(3)     D>                                   D>

                                                                                                                             y17    R         8                  y7    S0        8

                                             A                                                                             У2      C                           y6     C

                                                                                                        A0                 У5     >                            y5     >

   y4     C                              C                               П9           y5        A1                 y1     <                             y1    <

                                                                              Р14

    МК(0)                                         

                                                                                                                                      D   Tзн2                           D  Tзн1      

     МК(1)                                                           1                                                                             Р2                                     

                                                                                                                              у1     С                            у5     С

                                                              у5

                                                     Рис. 4.

                             RG3                          S3   АЛУ                            0    MS                   D   RG2                          D   RG1

                       D                     MK(2)     S2               F                      1                                 < > 0                               < > 0

                                               MK(1)     S1                                       2                           D<       1                          D<       1

                                               MK(0)     S0                                       3            МК(4)     D>                                   D>

                                                              A`                      P14                               y11    R         8                  y7    S0        8

                                                              B`               C9                                        У2      C                           y6     C

                                               MK(3)    C0                                      A0                 У3     >                            y3     >

               y4     C                                    M                            y3       A1                 y1     <                             y1     <

                                                                        y5        1

                                                                        y3

                                                                                                                 D   Tзн2                                               D  Tзн1      

                                                                                                                                   Р2                                     

                                                                                                         у1     С                                                 у3     С

                                                                                                                                                  1           D    T

                                                                                                                                         y3                

                                                                                                                                         y1       1          C                                                                                                      

                                                              Рис. 5.

          5. Функциональная схема управляющей части

   Функциональная схема УЧ устройства представлена на Рис. 8 и включает следующие основные части: триггер запуска (Тзап), управляющую память (УП), регистр адреса МК (RGAMK), схему формирования управляющих сигналов МО у1 - у12 , основу которой составляет дешифратор МК (DCMK), мультиплексор логических условий (MS) и триггер ошибки (Тош), который устанавливается в 1 при обнаружении ошибки в МК, считываемой из УП.

         Исходя из количества вершин в графе МП на Рис. 6 и ее сложности, определим ориентировочно количество ячеек в УП, равным 3 сегментам по 16 ячеек в каждом. Формат МК, записываемой в ячейке УП, приведен на Рис. 7.

                   MK                       Y                              XvSнов              A`       B  

            0    1   2    3    4  Q1 Q2 Q3 Q4 W  P                                                   к.р

                              Рис. 7

   Здесь старшие 9 разрядов образуют операционное поле МК. В первых 5 разрядах кодируются горизонтальным способом микроприказы МК(0 - 4),

                                                                     начало

                                                                                   4  

                                                                          a

                                                                  0               1                                  2  

                          y6                                                                                         6

                          y11                                                                           1    9

                                                                                                                  0  

                     0                                                    МК(1,2),2                   11                     МК(0),2

                            P5                                                                                

                               1                                                                          1  10   

                      МК(0),у2                                                                                  7

                                    0                          0                                             15     0 

                            P3                     P14                                                    1

                                 1                         1                                            1   12

                                     0                                                                                8

                            P1                                                                                       9

                           1                                                                             0    4

                 МК(4), y3, y9                          y3,  y9                                      3      

                                                                                                              1

                                                                                  МК(0),2                1                 МК(1,2),2                          

                     0                                                                                                         

                           P4                                                                                 7     0

Страницы: 1, 2, 3, 4